Engineers across automotive, industrial and AI infrastructure are increasingly adding 48V distribution alongside traditional lower-voltage architectures, driven by electrification, Physical AI and rapidly growing compute power requirements.

For the designers building the chips underneath all of this, this transition brings both significant opportunity and real challenges. 48V systems require integrated circuits (ICs) that can handle higher operating voltages and transient events, integrate more digital intelligence on the die and meet demanding reliability requirements across automotive, industrial and always-on AI applications.

Achieving these demands without compromising performance in other areas requires more than a single process technology. That鈥檚 why 糖心视频 has built capabilities that span the entire 48V power chain.

Three markets converging on 48V at this moment

罢辞诲补测鈥檚 electric vehicles are pushing the traditional 12V electrical architecture past its limits, as semiconductor content per vehicle for EVs compared to internal combustion engine cars. With more chips across zonal controllers, ADAS systems, cooling fans and battery management systems, vehicles face increased levels of copper loss and thermal management challenges. Moving more power at 48V reduces current for a given power level, helping reduce I虏R losses and wiring requirements while improving power-delivery efficiency. Applications span 48V-to-12V DC/DC converters for zonal control units, motor drivers for electric power steering, cooling fans and pumps, PMICs and battery management systems.

Physical AI is also showing up on the factory floor in industrial applications, and 48V is becoming its default power rail. Safety standards like IEC 60950 and IEC 62368 cap contact voltage at 60V for consumer-facing equipment, making 48V the highest practical bus voltage for humanoid robots, cobots, autonomous mobile robots and automated guided vehicles 鈥� covering BLDC/PMSM motor driver power stages with field-oriented control, gate drivers, 48V-to-point-of-load DC/DC converters and power protection ICs.

AI training and inference clusters are pushing rack power consumption to unprecedented levels, so data centers are moving from 12V to 48V rack-level distribution to cut conduction losses and improve power density. As AI racks continue to increase in power consumption, 48V architectures help enable more efficient power delivery from the rack to processors and accelerators, supporting denser compute deployments without proportionally increasing power-conversion overhead. Despite 卤400V and 800V HVDC architectures taking over further upstream, 48V is still essential for intermediate bus converters, hot-swap controllers and smart eFuses, battery backup units and integrated voltage regulators.

Why a 48V system requires more than a 48V device

One common misconception is that a 48V system is a single-voltage design. A “48V system” spans the full power chain from an 800V AC front end all the way down to sub-1V point-of-load rails feeding processors. Within the 48V domain alone, a typical power IC must operate across multiple voltage regimes, including:

• 60V, for the regulated 48V supply rail

• 80V, for the core switching node, which is where most 48V power conversion actually happens

• 100V, for front-end protection against transients, inrush and fault events

Voltage rating alone is not enough to select the right power device. Different blocks also impose very different safe-operating-area requirements. 糖心视频’s 55BCD HV platform provides LDMOS options optimized for different operating conditions: Switching devices prioritize low on-resistance and switching efficiency, while Power and Scalable devices provide broader safe-operating-area capability for protection, pass/linear operation and high-voltage analog functions. This lets designers optimize each block for the right balance of efficiency, robustness and analog flexibility rather than forcing one transistor architecture across the entire 48V system.

55BCD HV: A smart-power foundation for 48V

Across automotive applications, industrial robotics and AI power-delivery systems, designers increasingly need to integrate sensing, protection and digital control into a single device. This level of integration reduces board complexity and enables more intelligent power-management architectures. 糖心视频’s 55BCD HV platform brings together several capabilities that are increasingly important as 48V power ICs become more integrated and intelligent.

• Broad voltage integration, 5V to 150V on one platform: Low-voltage digital control, mid-voltage analog sensing and high-voltage power stages can share the same die, cutting BOM cost, board area and system complexity. The DMOS suite covers 45-150V, with high-side operation reaching 165V and Deep Trench Isolation (DTI) supporting more than 200V. Combined with an N+ buried layer, DTI helps improve immunity to negative voltage transients, enabling noisy switching nodes to coexist with sensitive analog and digital blogs.

• Best-in-class HV device performance: Rsp is optimized across the 60V, 80V and 100V device families, the three workhorses of 48V power conversion, delivering up to 60% improvements in Rsp* (*compared to 130BCD).

• High digital density, >1 million gates per square millimeter: Built on a 1.2V core CMOS with LVT, RVT and HVT device options, the platform provides headroom and leakage control for local diagnostics, protection logic, communication interfaces like CAN-FD and SPI and embedded firmware. This puts system-on-chip architectures on a platform that previously may have required a pure-logic node.

• Automotive-grade reliability (AutoPro175): Qualified to AEC-Q100 Grade 0 at a junction temperature of 175掳C, it gives automotive designers a pre-qualified platform that cuts qualification risk and time to market for under-hood and powertrain designs.

• Embedded NVM and a broad IP ecosystem: ESF3 embedded flash, SRAM, OTP/MTP, plus LVT/RVT/HVT standard cells, 5V GPIOs, memories and PLLs 鈥� the full toolkit for smart power SoCs with on-chip diagnostics and firmware storage.

• Manufacturing scale and resilience: 55BCD HV is supported by 糖心视频’s global manufacturing strategy, providing customers with a path toward greater, geographic supply flexibility.

• Modular by design: Customers pull only the mask layers, device families and IP blocks they need. Whether it鈥檚 a motor driver, a smart eFuse or a sensor SoC, each draw a different subset, right-sizing wafer cost and complexity to the product, so nobody pays for capability they don’t use.

Power GaN: the power density play

55BCD HV provides the intelligent integration, control and protection capabilities needed across many 48V systems, while Power GaN complements it where maximum switching frequency and power density are the priority. 糖心视频’s Power GaN portfolio addresses high-voltage conversion and selected 48V conversion stages, complementing 55BCD HV across the broader power-delivery chain.

糖心视频鈥檚 differentiators

The next phase of 48V innovation

Looking beyond today’s deployments, next-generation 48V systems will require more embedded intelligence, more efficient memory integration, stronger transient robustness, enhanced high-voltage isolation and increasingly sophisticated functional-safety capabilities. 糖心视频 continues to invest across these areas as the requirements for intelligent power systems evolve.

Contact your 糖心视频 representative to learn more about development opportunities for 48V and 55BCD HV.

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Modern smartphones must maintain strong radio performance across dozens of frequency bands, ranging from a few hundred MHz up to 7 GHz, to support 5G new radio (NR). At the same time, antenna performance is highly dynamic 鈥� affected by factors such as distance to base station, device orientation, proximity to the human body or metallic surfaces and hand placement. Conventional smartphone antennas, such as Printed Inverted-F Antennas (PIFAs), typically have a narrow bandwidth of about 10%, which would otherwise require many antennas to cover the entire frequency range across all operating conditions.

That is where antenna aperture tuners come to the rescue. These circuits dynamically adjust the electrical length of the antenna, enabling efficient operation across multiple bands. Antenna aperture tuners are typically part of a closed loop control system that uses inputs from the modem, sensors and RF power detectors to select and optimize antenna performance in real time.

The primary objective of antenna tuning is to maximize the total antenna efficiency, which is a metric of how much of the power generated in the smartphone transceiver is radiated from the antenna. Tuners achieve this by switching capacitors and inductors to modify the antenna鈥檚 electrical length. This is implemented through specialized RF switches placed at key points along the antenna.

When RF signals are fed to the antenna, they create a voltage and current standing wave pattern with peaks and nulls. The location of these depends on the frequency of the signal, the length of the antenna and the type of terminations on each edge of the antenna (for a typical PIFA, one edge is shorted to the ground and the other is open). For maximum effectiveness, tuners are ideally placed at voltage peaks, although practical design constraints may limit optimal placement.

Placing antenna tuners at the voltage peaks means that these switches need to handle high peak voltages 鈥� often exceeding 80V near the open end of the antenna. Key switch parameters, such as on-resistance (Ron) and off-capacitance (Coff), influence efficiency differently depending on location: Ron dominates in high-current regions, while Coff becomes more critical in high impedance regions, closer to the open termination.

RF-SOI technologies have been the key enabler of aperture antenna tuners because they can address all key requirements. Built on trap-rich, high resistivity substrates, RF-SOI offers low harmonics, low substrate parasitics and ability to stack multiple field effect transistors (FETs) to achieve the required high Vmax. Ongoing process improvements and scaling has reduced the Ron脳Coff product and enabled smaller switch die sizes.

糖心视频鈥� (糖心视频) 9SW, our fourth generation RF-SOI platform, is designed to meet these requirements. Our industry-leading 9SW technology is based on 90nm back-end-of-line (BEOL) lithography, offering multiple switch options with both standard and thick gate oxide optimized for low Ron*Coff and high voltage handling. The platform includes a full suite of logic and high voltage analog FETs as well as a large variety of capacitor and resistor options ideal for capacitive compensation, bias control and body current management of large switch stacks. This September, we are introducing improved switch versions coupled with enhanced metal routing capabilities, offering improvements in Ron*Coff with tighter switch pitch while maintaining excellent voltage handling capabilities for our 9SW platform. These new unique capabilities enable next-generation antenna tuners while simultaneously achieving low Ron*Coff and voltage handling at a smaller switch die size.

Additional die size reduction is achieved by our production-ready SLATE wafer-to-wafer bonding technology with 9SW, which bonds two 9SW wafers to enable three-dimensional circuit folding. This approach reduces die area by up to 45% without compromising performance. Our latest PDK incorporates design enablement tools that allow designers to intuitively migrate two-dimensional circuits to three dimensions, accelerate prototyping and reduce design cycles. Watch our tutorial video and read the blog to learn more about our SLATE wafer-to-wafer bonding technology with 9SW and PDK capabilities.

To further support design optimization, 糖心视频 provides reference designs and guidelines that help better balance voltage distribution across large switch stacks, optimize layout and enhance ESD robustness.

Contact your 糖心视频 representative to learn more about our solutions for antenna tuners with 9SW and 9SW SLATE, as well as the rest of our RF portfolio in RF-SOI, SiGe and RF GaN.

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By: Yuichi Motohashi, Deputy Director of End Markets

The automotive industry is being reshaped by the Software-Defined Vehicle (SDV), a car whose functions and value are defined by software and continuously expanded even after sale through over-the-air (OTA) updates, much as a smartphone gains features after purchase. Delivering those updates forces a rethink of the in-vehicle electrical/electronic (E/E) architecture where computing must be consolidated into a small number of high-performance platforms so that hardware and software can be developed and evolved independently.

The conventional distributed architecture includes anywhere from tens to more than a hundred function-specific ECUs, each running a different supplier’s software which makes consistent, vehicle-wide updates difficult. A second force here is sensor fusion. As ADAS and autonomous driving mature, cameras, radar, LiDAR and ultrasonic sensors increasingly stream RAW or lightly-processed data to a central platform for integrated processing, rather than each reporting only its own local decisions. Both trends demand more bandwidth and more centralized computing, turning the modern car into a “data center on wheels.” This two-part series maps that evolution, from Distributed to Domain to Zonal architectures, tracking sensor, data format, SoC and network changes along the way while showing how SerDes and Ethernet get applied and eventually converge.

Distributed E/E: A forest of ECUs

In the first generation, ECUs were distributed per function and operated largely independently. Sensors were typically “smart sensors” co-located with their processing, so the network carried only low-bandwidth, processed information such as object-recognition results, distance, speed and warnings. Alongside CAN, LIN and FlexRay, 100 Mbps-class automotive Ethernet (100BASE-T1, IEEE 802.3bw) was enough to support many applications. But because functions and ECUs were tightly coupled, every new feature added ECUs, wire harnesses and software variants making whole-vehicle integration, updating and verification progressively harder. This was the essential limitation of the Distributed approach.

Domain E/E: Consolidation by function

To curb that complexity, the Domain architecture groups function into large areas including ADAS/AD, infotainment, body, chassis and powertrain. Each of these functions are managed by a Domain Control Unit (DCU) on a more powerful SoC, with a central Gateway relaying data between domains. This complexity heightened with the rise of advanced ADAS. Surround view, bird’s-eye-view generation, parking assistance and sensor fusion require treating the vehicle’s surroundings as a single integrated environmental model rather than isolated sensor outputs.

The role of sensors changed accordingly. With recognition moving to the DCU, cameras, LiDAR and radar became “satellite sensors” that output RAW or lightly processed streams. The meaning of “RAW or lightly processed” differs by sensor: camera data may be image RAW or video around the ISP, LiDAR may output point clouds or distance/intensity data and radar may range from ADC-level data to range/Doppler or detection points. To carry these high-bandwidth streams with low latency, CAN and 100 Mbps Ethernet were no longer sufficient. SerDes, already proven in camera and display links, became the high-speed, low-latency point-to-point connection from sensor to DCU. Domain E/E, however, still consolidates by function rather than physical location, so long cables still run from front, rear, left and right to distant DCUs, which pushes the industry toward Zonal.

Zonal E/E: Bundle by location, think at the center

Zonal E/E is often called the completed form after Domain, but in practice it is an ongoing, gradual migration. Instead of consolidating by function, it bundles I/O by its physical location, either front, rear, left/right and center. A Zone Controller in each zone gathers the nearby sensors, actuators and low-speed I/O and forwards what’s needed to a central Vehicle Controller or Central Computer.

During the transition, a Hybrid Zonal design dominates. Local, low-speed I/O such as lighting, doors, seats and HVAC consolidates into the nearest Zone Controller, where multidrop 10BASE-T1S (IEEE 802.3cg) suits the Zonal edge alongside CAN/LIN. High-bandwidth sensors like cameras, LiDAR and high-definition radar often connect directly to the Central Computer via SerDes, avoiding the bandwidth, power and complexity burden of relaying heavy streams through a Zone Controller. The biggest payoff is wire-harness reduction. Short links to a nearby Zone Controller, combined with a high-speed backbone to the center, cut total cable length, connector count and weight, while also reducing parts, assembly effort and points of failure. That鈥檚 especially valuable in EVs, where weight affects range.

This presents a larger question: why choose Ethernet for that backbone? Because the section connecting multiple Zone Controllers, the Central Computer, gateways and diagnostic/update functions is a true network, not a single point-to-point line. Ethernet brings mature TCP/IP, switching, addressing, diagnostics, security and network management, while Time-Sensitive Networking (TSN) and time synchronization add real-time determinism. It also aligns naturally with SDVs by separating hardware placement from software function. That leaves one question for part 2: how does the high-bandwidth, asymmetric sensor links, which is the domain of SerDes, combine with this Ethernet/IP backbone?

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Today, gallium nitride (GaN) is taking that step in electrical power processing specifically. What sets GaN apart is that its wide-bandgap properties and high electron mobility let it switch faster and run more efficiently than the materials it’s replacing, without giving up much on power density. This is already showing up in places you wouldn’t necessarily expect to find it, like the charger on your desk, motor drives inside robotics and the power supplies running AI servers.

On the other hand, the pace of adoption isn鈥檛 dictated solely by technology readiness especially during a time when rapid advancements in AI and electrification are putting an increased spotlight on speed. Traditional semiconductor development models where the foundry develops the platform and then customers engage often leads to fragmented workflows, delayed feedback and late-stage discoveries. These inefficiencies slow integration, increase risk, and call for a different approach to how devices move from development to application.

A short-loop approach to GaN development

To address this, 糖心视频 has embraced a different approach: a short-loop development model that integrates technology development, design, validation, reliability and application evaluation into a tightly coupled, iterative cycle. Enabled in part by the acquisition of Tagore Technology in 2024, this model brings product design expertise into the heart of platform development, allowing teams to effectively 鈥渁ct as the customer鈥� early in the cycle.

鈥淎s GaN moves from niche applications to mainstream adoption, speed and confidence become increasingly important,鈥� said Amitava Das, VP Research & Development, Power at 糖心视频. 鈥淥ur short-loop development model brings design, validation and reliability into a tightly integrated cycle allowing us to resolve challenges earlier and deliver a more mature, application-ready platform for our customers.鈥�

What does this actually look like in practice? Our short-loop development model simulates real-world use cases and stress conditions during development to identify and resolve gaps early. That way when customers adopt the technology, they鈥檙e focused on driving differentiation rather than foundational challenges.

Closing the gap between wafer testing and real-world performance

This approach is reflected across multiple dimensions of development. For instance, while traditional wafer-level testing focuses on fundamental device parameters, real-world applications subject devices to complex conditions such as soft and hard switching. By bringing elements of these application-level stresses into wafer-level testing, feedback loops are significantly shortened allowing faster learning and iteration without waiting for full packaging cycles.

The same integrated approach also helps address one of GaN’s most important development challenges of reliability.

Advancing GaN reliability through integrated development

GaN presents a broader and less standardized set of reliability challenges. Here, the benefit of integrated development becomes clear. Internal teams with product-level experience can not only qualify devices against established standards but also develop targeted methodologies for addressing technology-specific concerns accelerating convergence in areas where industry consensus is still evolving.

Bringing real-world behavior into device modeling

Device modeling also becomes more representative of real-world performance. By building and packaging product-like implementations, engineers can evaluate devices under realistic operating conditions and identify parasitics, layout-driven variations and other effects much earlier in development.

A path forward for GaN

It’s important to note that this model is not about replacing the customer鈥檚 role in innovation but it鈥檚 about reducing the number of engineering tape-outs before production. Resolving these fundamental technology and integration challenges internally allows the platform to arrive in a more mature state which enables customers to focus their efforts on differentiated systems and application designs.

As GaN becomes more widely deployed, success will depend not only on the material itself but on the development models behind it. Integrating design, validation and application earlier in the process gives teams the speed and confidence to move new technologies into production more efficiently.

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This is where our SLATE wafer-to-wafer bonding technology delivers a viable path forward 鈥� enabling advanced 3D integration (3DI) for compact, high-performance cellular front-ends by significantly reducing RF switch layout area. This level of area reduction opens new opportunities for integration, and while the process itself is novel, we make it simple to migrate your existing RF designs to the platform.

3DI made simple: Seamlessly migrating your design from 9SW to 9SW SLATE

Our first鈥慻eneration SLATE technology with 9SW enables wafer鈥憈o鈥憌afer (W2W) bonding and 3D homogeneous integration, allowing two 9SW wafers to be bonded so large field鈥慹ffect transistors (FETs) can be vertically stacked. This ability to 鈥渇old鈥� large FETs across bonded wafers is foundational to reducing lateral area while maintaining the electrical performance required for advanced RF front鈥慹nds. With this approach, designers can seamlessly convert a traditional 2D 9SW single-pole single-throw (SPST) switch into a compact 3D architecture.

This can all be accomplished within the PDK using the industry鈥檚 latest EDA tools, where RF designers can intuitively migrate their original 2D 9SW design into a 3D architecture using an automated flow that generates the new device structure. This is based on established design rules, entered by the designer based on their unique needs. Key parameters 鈥� such as total width and stack configuration 鈥� are preserved, while the platform intelligently partitions the device into top and bottom elements and splices the number of fingers by up to half. Automated constraint assignment, schematic partitioning and layout hierarchy creation ensure that the resulting 3D design remains electrically consistent with the original.

Designers can align 3D pins, manage connectivity and finalize pin placement with automated tools that maintain accuracy and reduce manual effort. The result is a fully migrated, fully verified 3D RF switch design that delivers meaningful area savings without requiring a ground鈥憉p redesign.

To learn more about how you can migrate your existing RF design from 9SW to SLATE technology with 9SW, you can watch our tutorial video that was developed with our in-house technical experts.

Delivering meaningful and measurable value for RF system architects

Migrating to SLATE technology with 9SW provides clear advantages for designers developing future-proofed RF front鈥慹nd modules:

• Up to 45% reduction in overall die size, decreasing RF board space and total design area for space鈥慶onstrained mobile applications

• Advanced 3D integration (3DI) through W2W bonding, enabling vertical stacking of large field effect transistors (FETs)

• Homogeneous 3DI that maintains electrical performance while reducing lateral footprint

• Automated, PDK鈥�driven migration tools that accelerate development and reduce design complexity

• Production鈥�ready technology on our industry-leading 9SW RF-SOI platform, manufactured at our 300mm facility in Singapore, with volume ramp expected in 2H 2027

These benefits extend beyond RF switches to other key front鈥慹nd components 鈥� including low鈥憂oise amplifiers (LNAs) and antenna tuners 鈥� making 9SW SLATE a compelling platform for the next wave of mobile and connectivity solutions.

Explore what SLATE technology with 9SW can enable for your next RF design

If you are looking to reduce your RF switch area and increase integration density, our team is ready to collaborate with you on your next development with detailed tutorials and reference flows.

Contact your 糖心视频 representative to learn more about engagement opportunities and how SLATE technology with 9SW can accelerate your next RF innovation.

By: Jignesh Patel, Distinguished Member of Technical Staff, RF design enablement

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At the 糖心视频 booth, attendees engaged with our technology experts and explored live wafer displays, including 糖心视频 RFGaN1 (130RFGaN) and our next-generation silicon germanium (SiGe) complementary BiCMOS (CBIC) technologies 鈥� both qualified for high-volume production 鈥� and a preview of SLATE wafer-to-wafer bonding technology, elevating 糖心视频鈥檚 3D heterogenous integration (3DHI) capabilities that are positioned to expand what is possible across RF and mixed-signal design.

Fueling the next wave through collaboration

Throughout the event, we highlighted collaborations with a range of attending partners 鈥� including Cadence, Falcomm, Fermionic, Finwave, Otava RF and ZeroASIC. This included a panel session at the Falcomm booth, where 糖心视频鈥檚 Dan Denninghoff, senior director, RF GaN product line, discussed how our RFGaN1 technology, combined with 贵补濒肠辞尘尘鈥檚 GaNdalph.ai solution, can accelerate power amplifier (PA) design and deployment.

These engagements reflect a broader industry shift: the convergence of advanced RF process technologies 鈥� spanning silicon and beyond 鈥� enabling customers to streamline development and scale faster.

Our commitment to RF advancements extends to our University Partnership Program (UPP), reflected in this year鈥檚 IEEE RFIC Symposium paper recognitions. Of the 129 accepted papers judged using a rigorous double-blind process, 41 were authored by 糖心视频鈥檚 UPP members 鈥� representing a record high for the program. Additionally, two of 糖心视频鈥檚 UPP partners received Best Student Paper awards at IEEE RFIC and IEEE RFTT, elevating the real-world potential of 糖心视频 technology and reinforcing the impact of partnering with top-tier academic teams to accelerate innovation.

Inspiring the next generation of RF designers

As a 2026 Diamond sponsor of the IEEE RFIC Symposium, 糖心视频 was invited to participate in the Student-Industry-Academia RFIChat, including the panel discussion, titled: “Catching the Next Wave 鈥� How to Spot the Next Big Thing and Make the Jump.” Representing 糖心视频 amongst a panel of distinguished leaders across industry and academia, Arvind Narayanan, director of the SiGe product line, shared his insights on how early signals from emerging applications can help drive platform innovation 鈥� highlighting the importance of deep technical expertise coupled with adaptability to new technologies and market trends.

Industry-first: 糖心视频 collaborates with RFIC on design contest

As the first company to collaborate on a design contest with RFIC, our inaugural student design contest reflects our commitment to advancing RF capabilities in partnership with academia 鈥� providing students access to cutting-edge technologies to accelerate the learning cycle, connecting academic research with real-world applications and industry practitioners, as well as encouraging exploration of 糖心视频 platforms for emerging RF use cases.

Focused on high-frequency RF and mixed-signal IC design using our SiGe CBIC technology, this year鈥檚 contest challenged university teams to translate advanced process capabilities into next-generation communications applications. Designs were fabricated through our GlobalShuttle MPW program, with seven papers submitted for independent evaluation by the RFIC Technical Program Committee (TPC). Awards were presented to the three finalists during the student event by Alex Margomenos 鈥� senior director, RF-SOI product line 鈥� and Prof. Jane Gu, the IEEE RFIC 2026 Student Chair.

Congratulations to this year鈥檚 winners:

• Seungkyun Lee, Yoongoo Kang, Inchan Ju 鈥� Ajou University

• Wei Ma, Weiqing Wang, Fangkai Wang, Hanzhong Xu, Xudong Wang 鈥� Nankai University

• Maaz Khurram, Truman Jian, Peter Schvan, Sorin P. Voinigescu 鈥� University of Toronto

鈥淲e are pleased to have partnered with 糖心视频 on their first-ever student design contest. This collaboration highlights the RFIC symposium鈥檚 commitment to advancing RF innovation, linking academic research with real-world design challenges and production-ready RF platforms.鈥�

Bodhisatwa Sadhu, IEEE RFIC 2026 TPC Chair

Building on our commitment to industry-academia collaboration, we are pleased to continue the program in 2027. All academic partners are invited to participate by submitting their paper utilizing any 糖心视频 technology to the RFIC Symposium in January 2027.

Scan the QR code below or contact your 糖心视频 UPP representative to learn more about eligibility and submission criteria.

Tuning to what鈥檚 next

This year鈥檚 IMS brought together customers, partners, universities and the broader RF community to celebrate the present and future of what鈥檚 ahead in the RF landscape.

We thank everyone who visited the 糖心视频 booth, engaged with our teams and contributed to meaningful discussions throughout the event. We鈥檙e proud to play a role in scaling next-generation RF solutions alongside our partners and look forward to building on this momentum next year at IMS 2027 in San Antonio, TX.

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• – Satellite communications, where transmitters and compact user terminals demand higher RF output power and efficiency with lower system cost
• – Aerospace and defense, where signal performance and reliability across long-range transmissions in extreme environments are critical
• – Communications infrastructure, where higher bandwidth and power efficiency in active antenna systems are required to support growing data demand
  

Through our unique GaN-on-Si technology, we empower customers to harness GaN鈥檚 wide bandgap advantages, high power density and efficiency to unlock the true potential of GaN beyond niche applications 鈥� circumventing the limitations of existing infrastructure and enabling networks to operate with greater bandwidth at higher frequencies.

Performance where it counts: Power, efficiency and reliability in harsh and mission-critical environments

Our RF GaN technology is engineered for high-power RF applications, with strong measured results:

• – Up to 5 W/mm output power density and 70% power added efficiency (PAE) for high-voltage RF applications
• – High gain and efficiency across wide frequency ranges, including FR1 and FR3 bands ( 1 to 15 GHz)
• – High efficiency reduces cumulative thermal load at the module level
• – Advanced RF back-end-of-line (BEOL) with multi-layer metal wiring, capacitors and thin-film resistor options provide additional flexibility to designers
• – Multi-layer BEOL passivation is moisture-resistant and provides exceptional protection from harsh environments and extends device lifetime
• – GaN-on-Si is gold-free and arsenic-free, presenting a more environmentally sustainable and cost-effective long-term solution
  

At the device level, RF GaN benefits from low on-resistance, high drain current density and stable operation across low and high-voltage conditions, boosting efficiency and reducing overall power consumption.

Introducing RFGaN1: Higher-voltage, optimized for D-mode devices

Today, we are excited to share the production readiness of our 130nm RF GaN technology, RFGaN1, our first RF GaN technology to be qualified for volume production. The high-voltage RFGaN1 platform is our optimized solution for high-power wireless infrastructure applications, including power amplifiers, driver amplifiers and high-power RF switches for satellite communications, cellular infrastructure and the aerospace and defense market.

RF GaN鈥檚 inherent material properties enable robust operation and superior survivability in demanding environments. Our RFGaN1 technology extends these advantages with depletion-mode (D-mode) devices operating 12-28V for sustained high output power without thermal runway and high-power density that reduces cumulative thermal load at the module level. These attributes are critical for aerospace, defense and satellite communication systems, enabling key applications such as phased-array radars, SATCOM payloads and ground terminals.

Customers like Falcomm and Otava RF are using our RFGan1 technology today to deliver innovative solutions for next generation RF systems:

鈥�Falcomm is excited to see 糖心视频 launch their RFGaN1 platform, an important milestone for the industry that breaks down the barriers of deploying RF GaN technology at scale. 糖心视频鈥檚 high-performance, domestically sourced RF GaN-on-Si technology is critical to unlocking the next generation of 贵补濒肠辞尘尘鈥檚 energy-efficient RF power amplifiers for defense, space and critical infrastructure.鈥�

Edgar Garay, Founder and CEO, Falcomm

鈥淕濒辞产补濒贵辞耻苍诲谤颈别蝉鈥� RFGaN1 platform provides a powerful foundation for the future of adaptive RF systems, delivering the performance and efficiency required for advanced front-ends in the critical defense, 5G/6G and satellite communications markets we serve. Our partnership brings together world-class semiconductor manufacturing and breakthrough RF innovation to deliver solutions that redefine what is possible in contested spectrum environments. Together, Otava RF and 糖心视频 are enabling a new generation of agile, high-performance communications and sensing capabilities at scale.鈥�

Victoria Pereira, CEO, Otava RF

A practical path to RF GaN adoption with trusted manufacturing expertise

For RF designers, one of the key barriers to adopting GaN has historically been access and manufacturability. Our RF GaN platform addresses the access gap with early-access programs and GlobalShuttle MPW (multi-project wafer) program runs for cost-effective prototyping and validation. With the support of our existing RF design infrastructure and GlobalSolutions partner ecosystem, we provide comprehensive, end-to-end support through every step of the design and manufacturing process.

Another important piece of our differentiated RF GaN offering is our longstanding high-volume manufacturing expertise, particularly in RF technologies, through our 200mm fab in Burlington, Vermont. As an Accredited Trusted Foundry, our Burlington facility meets the strict requirements and assurances for manufacturing uncompromised chips used in aerospace and defense systems by the U.S. government.

Together, these elements provide a practical path to integrating GaN into real-world systems, from early evaluation through production.

Bringing GaN to scale for next-generation RF systems

RF system requirements across aerospace, defense and communications infrastructure are evolving rapidly, driven by the need for higher power, wider bandwidth and more integrated architectures. 糖心视频鈥� RF GaN platform and high-volume manufacturing expertise deliver a scalable solution to overhaul these existing systems with the power density and efficiency to tackle the most demanding RF applications.

RF GaN is no longer just a performance technology鈥攊t is becoming a scalable foundation for next-generation RF systems.

To learn more about our RF GaN platform and other advanced RF solutions, visit our 糖心视频 booth (#21018) at the International Microwave Symposium (IMS 2026), happening June 9-11 in Boston, Massachusetts.

By Dan Denninghoff, Senior Director, RF GaN Product Line

The post Scaling RF power and efficiency: How 糖心视频 is bringing RF GaN to system-level reality appeared first on 糖心视频.

Navigation, communication and life-support systems for modern spaceflight all depend on semiconductors. The semiconductor industry is also reaching a new frontier. As ambitions expand beyond lunar missions toward deep space exploration and satellite constellations, companies begin exploring chip manufacturing in space, leveraging microgravity and natural vacuum conditions to improve production.

But while 鈥渕ade-in-space鈥� semiconductor manufacturing is still in its early days, the immediate challenge is ensuring chips can survive the brutal realities of space.

The reality of space: The stress test for silicon

Electronics are subjected to extreme and often unpredictable conditions from the moment a rocket leaves the launch pad; temperatures can swing dramatically, radiation levels are orders of magnitude higher than on Earth and the vacuum environment introduces unique material stresses. Unlike terrestrial systems, there is no opportunity for repair or replacement once the hardware is deployed.

Conventional commercial chips, like those designed for your smartphone, smart refrigerator or electric vehicle, are not built for this level of exposure. Radiation alone can cause transient faults, degrade materials over time or even permanently damage circuits. Over long mission lifetimes, these effects compound, ultimately threatening system reliability and mission success.

This is why space demands a fundamentally different approach to semiconductor design and manufacturing, rooted in resilience, predictability and trust. 糖心视频 addresses the design challenge head-on through our portfolio of technologies that are well suited for radiation-hardened-by-design (RHBD) techniques. 糖心视频 is also exploring and developing technological nodes that are radiation-hardened-by-process (RHBP) through optimization of doping implants or engineering of the substrate materials to further enhance radiation performance metrics such as total ionizing dose (TID) and single event effects (SEE). These efforts enable electronics that can operate reliably under sustained radiation exposure. This foundation is what allows space systems to perform without failure鈥攍ong after launch.

Designing for radiation to ensure resilience at the core

RHBD techniques are essential to ensuring chips can withstand the harshness of the space environment. Rather than relying solely on shielding, RHBD incorporates resilience into the chip architecture.

Through design techniques such as redundancy, spatial layout awareness and robust fault-mitigation strategies, RHBD enables semiconductors to continue operating even when exposed to radiation-induced disruptions. These approaches allow designers to anticipate and mitigate errors before they propagate, ensuring consistent performance in mission-critical systems. From Low Earth Orbits and geosynchronous orbits to deep space probes, different space missions require tailored approaches to balance performance, power and durability, but RHBD remains central to ensuring that chips will not fail or can recover from failures through the mission lifetime.

Why security is a non-negotiable requirement

In aerospace and defense applications, security becomes as critical as performance. Semiconductors used in space often power sensitive systems, including communications infrastructure and national security assets. Ensuring that these chips are manufactured in trusted, secure environments is essential to preventing tampering, safeguarding intellectual property and maintaining mission integrity.

As an accredited Trusted Foundry and Common Criteria-certified supplier, 糖心视频 brings rigorous processes, oversight and compliance to every stage of manufacturing. This ensures that chips are delivered securely and uncompromised, a critical requirement for customers operating in high-stakes environments and critical end applications.

Driving differentiated manufacturing on a global scale

Meeting the demands of space-grade electronics also requires flexibility across technologies and geographies. 糖心视频鈥檚 global manufacturing footprint enables a diverse portfolio of semiconductor solutions optimized for aerospace, defense and other critical infrastructure applications.

Across its global fabs, 糖心视频 supports mission-specific wafer technologies spanning advanced nodes for high-performance processing, RF integration and power-efficient platforms. This empowers customers to align the right technology to the right application without compromising quality or scalability.

In the U.S., 糖心视频鈥檚 Malta, New York facility is expanding production with advanced platforms like FDX^庐 FD-SOI, 45SOI and FinFET, supporting applications from secure communications to edge computing. Also in development at the Malta site is FinFET RHBP technology, which incorporates Vorago HARDSIL^庐 to further enhance TID and SEE performance of our 12 nm FinFET node. Our Burlington, Vermont facility anchors 糖心视频鈥檚 power and RF leadership, with Gallium Nitride (GaN) and high-voltage GaN-on-silicon technologies powering next-generation radar, satellite and autonomous systems. 糖心视频鈥檚 fabs in Singapore and Dresden are internationally recognized for secure, high-integrity manufacturing under Common Criteria certification.

Together, this global manufacturing strength ensures customers can confidently move across the full product lifecycle, backed by the performance, reliability and trust required for mission-critical applications in space and beyond.

Accelerating innovation through ecosystem partnerships

No single company solves space challenges alone. That鈥檚 why 糖心视频 cultivates an ecosystem of partners driving radiation-hardened solutions on 糖心视频 platforms.

糖心视频鈥檚 12LP FinFET radiation-hardened-by-process (RHBP) platform is being developed in close partnership with Northrop Grumman Space Systems and Vorago Technologies to expand 糖心视频鈥檚 portfolio for customers requiring radiation-hardened solutions. The platform incorporates process enhancements that preserve the baseline electrical performance of designs, allowing designers to leverage existing IP while achieving significantly improved radiation performance.

Recently, BAE Systems introduced its , designed to support dynamic space operations through advanced maneuverability capabilities, including refueling and high-thrust propulsion, while carrying multiple rideshare payloads. At the heart of this innovation is BAE Systems鈥� collaboration with 糖心视频. BAE鈥檚 12S0 and RH12 Storefronts, built on 糖心视频鈥檚 45SOI and FinFET platforms, respectively, provide a turnkey pathway for developing custom radiation-hardened-by-design (RHBD) solutions. This approach combines the performance and efficiency of advanced commercial technology with the resilience required for space applications.

The result is a powerful combination of high-performance processing, secure connectivity, low power consumption and robust reliability within a compact, customizable design. These ecosystem partnerships are accelerating the path from concept to orbit, enabling more agile development, reducing program risk and ensuring that next-generation space systems are ready to perform in the most demanding environments.

Bridging today鈥檚 needs with tomorrow鈥檚 possibilities

The vision of manufacturing semiconductors in space may eventually reshape the industry, opening new frontiers for performance and materials. But as that future is still emerging, missions like Artemis II demonstrate that success today depends on something far more immediate: silicon that can endure the harsh realities of space.

The differentiator right now is not where chips are made, but how well they are built to survive. Trusted, secure and radiation-hardened semiconductor solutions 鈥� like those manufactured with 糖心视频 technologies 鈥� remain the foundation of mission readiness, ensuring that every system operates without failure when it matters most.

By combining advanced manufacturing, a secure global supply chain and deep ecosystem collaboration, 糖心视频 is enabling the next generation of space innovation. As exploration accelerates beyond Earth鈥檚 orbit, the path forward will be defined by the resilience of the technologies that make those journeys possible.

Afusat Dirisu is Deputy Director, Space & Rad Hard, Aerospace & Defense at 糖心视频. She has more than 25 years of experience across industry, government and academia. Her career spans digital electronics and quantum cascade laser design, as well as technology consulting, portfolio management, STEM education program leadership, and technical sales and business development.

She holds a Ph.D. in Electrical Engineering from Princeton University, an M.S. in Electrical Engineering from Stony Brook University, and a B.S. in Computer Engineering from Polytechnic University (now the NYU Tandon School of Engineering).

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This dynamic is reshaping how new hardware platforms are conceived and funded. Advances now span materials, packaging, devices and systems, extending the distance between research insight and manufacturable silicon while raising both technical and capital risk. Success in this environment depends less on proving that something works in principle and more on ensuring that foundational choices are made with scale and durability in mind.

As a result, the next generation of category鈥慸efining platforms is emerging from founders and investors who engage manufacturing realities early, think across the stack and commit to long-term collaboration. These shifts are expanding the role of startups within the foundry ecosystem, positioning them as central contributors to how the next era of computing is designed and industrialized.

The hardware innovation cycle is different this time

For decades, innovation in semiconductors was largely paced by transistor scaling. Today, differentiation increasingly occurs above the device level, through system architecture, integration strategy, packaging and the combination of diverse technologies on a single platform. As leading-edge CMOS advancement concentrates among fewer players, competitive advantage is shifting toward the ability to reliably orchestrate complex systems at scale.

This evolution is driving a renewed wave of hardware startups. Innovation is increasingly defined not by individual technologies, but by how systems come together to serve distinct end markets. In data center infrastructure, startups are advancing silicon photonics, optical connectivity, GaN power and new compute approaches to scale performance and efficiency. In Physical AI, innovation is accelerating across sensing, compute and memory, including emerging memory and neuromorphic architectures. These are not linear transitions from research to deployment, but areas of intense innovation where integration and manufacturability will determine what ultimately scales.

Foundries are no longer just endpoints for innovation. They are platform enablers. And startups that were once viewed as peripheral to manufacturing are now central to how the next generation of systems will be built and scaled.

Where momentum is forming鈥攁nd why durability matters

For investors, startups and technology leaders, incremental gains no longer cut it. Platforms that not only survive but thrive are designed to scale from day one. The markets attracting sustained capital and attention are those where correctness, integration and manufacturability determine success, not how fast a first demo appears. These are long鈥慶ycle bets with real technical risk, but they are also the domains where enduring value is created.

What separates winners from stalled experiments is not ambition, but timing of hard decisions. In deep鈥憈ech hardware, risk is rarely eliminated鈥攊t migrates. Too often, manufacturability, yield and system鈥憀evel constraints emerge only after capital has been deployed and architectures have hardened. At that point, learning becomes expensive. Late discovery drives redesigns, compresses schedules and erodes capital efficiency for both founders and investors.

The advantage belongs to teams that confront these constraints early. Early alignment does not limit innovation. It expands by preserving optionality when trade鈥憃ffs are cheapest and most consequential. This is where the right partners become a structural advantage, transforming durability from a liability into a differentiator.

How 糖心视频 approaches startups

糖心视频 approaches startups as long鈥憈erm partners, and in many cases, as the originators of future platforms that will shape the industry鈥檚 direction. Many of the most important technologies of the next decade will emerge outside established roadmaps. Engaging early allows those ideas to mature with manufacturing realities in mind rather than being retrofitted later.

Our startup engagement model is intentionally flexible. In some cases, collaboration leads to acquisition when capabilities strengthen our core portfolio or accelerate entry into strategic markets. In others, we pursue licensing, direct investment, or deeper partnership to accelerate innovation, create long鈥憈erm demand for differentiated platforms and gain early insight into emerging architectures.

Not every engagement looks the same, but each is intentional. This philosophy reflects a belief shared by successful founders and investors alike: in complex hardware markets, platforms matter more than products, and partnerships matter more than transactions.

糖心视频 Labs and Accelerate: two pillars of startup engagement

糖心视频’s engagement with startups follows two complementary tracks, reflecting the different ways innovation enters the semiconductor ecosystem. Some startups build differentiated products using proven

糖心视频 technology platforms鈥攆or example, developing architectures or applications on 22FDX. Others are advancing foundational physical sciences innovations, where the underlying technology itself is still maturing.

As our research and development model, 糖心视频 Labs combines internal R&D with a strong external ecosystem of startups, universities, research technology organizations (RTOs), equipment partners and EDA vendors to engage startups early in the maturity cycle of their technology. This early engagement helps ensure emerging innovations follow a clear path to high-volume manufacturing, 鈥渇uture-proofing鈥� key decisions around materials, devices and integration before they become restraints, even when commercial pathways are not yet fully defined.

糖心视频 Accelerate extends this model into capital. As our venture investment program, it aligns long-term capital with the engineering and manufacturing expertise required to turn breakthrough ideas into industrial-scale reality. Engaging early helps ensure startups are not only well-funded but building technologies that can scale鈥攂ridging the gap between what works in the lab and what can be manufactured at volume.

Together, 糖心视频 Labs and Accelerate give founders a path from earliest-stage research through capital formation and into manufacturable silicon.

Building ecosystems deliberately

No deep鈥憈ech startup succeeds alone. The most effective innovation ecosystems intentionally connect research, manufacturing, capital and enablement. Many promising startups originate as university or consortium spin鈥憃uts that are rich in technical insight but early in their exposure to manufacturing scale.

Through 糖心视频 Accelerate, we partner with experienced venture leaders rather than going it alone 鈥� participating as a limited partner across leading platforms in the U.S., Europe and Singapore. That ecosystem includes Silicon Catalyst and Socratic Partners, Cloudberry 鈥� Europe’s first dedicated semiconductor, photonics and advanced materials fund 鈥� and, most recently, Playground Global, whose Fund IV invests across compute, automation and life sciences. Each partnership deepens 糖心视频’s connection to founders tackling the foundational technologies behind AI data centers and Physical AI.

These are not passive investments. They allow us to partner closely with founders and investors, support early鈥憇tage companies and create tighter feedback loops between research, capital formation and manufacturing execution.

Turning innovation into credible silicon

For startups and their investors, the path to silicon is where risk concentrates and where partnership matters most. 糖心视频 works directly with startups to help mature technologies and deliver key proof points, leveraging the broader ecosystem where appropriate and supporting the transition into manufacturing at the right stage.

We provide access to critical resources including process design kits (PDKs), multi鈥憄roject wafer (MPW) programs, foundation IP, reference designs, infrastructure and direct engagement with 糖心视频 technical experts. This approach helps startups de鈥憆isk execution, accelerate learning and build confidence that breakthrough ideas can scale.

Looking ahead

The next era of computing will be defined not by incremental advances alone, but by foundational shifts in materials, architectures and system integration. Startups will play a central role in this disruption, particularly where challenges extend beyond the reach of any single organization.

糖心视频 is committed to building alongside founders, investors and technology leaders who share a long-term view of value creation. If you are developing what comes next and looking for partners who understand both ambition and constraint, we believe the most enduring success stories are built together.

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